DFT - 芯片验证/硬件加速仿真实习生 (Jul - Dec 2025)

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ （如已在BOSS直聘投递，请勿在此重复投递） THE ROLE: This engineer plays a key role in SoC DV and Emulation flow, he/she will mainly focus on emulation model based testbench development and emulation test case verification to accelerate long run time simulation tasks in pre-silicon design stage. Moreover, he/she is expected to support post-silicon validation team to enable the silicon debug feature for silicon bring up tasks. THE PERSON: Good team worker with solid Verilog RTL design and verification knowledge/experience. Knowledge reservation on System_Verilog/UVM/Modeling/Scan/BIST will be a strong plus. KEY RESPONSIBILITIES: Cutting-edge test strategies study and implementation. SoC level DFT emulation testbench setup and maintenance Responsible for emulation model development and Pre-silicon test case simulation. Support Post-silicon validation bring up/debug tasks. Support part of SoC DFX DV verification tasks. Generate and maintain SoC DFT Emulation Checklist, keep enhancing emulation flow maturity. Co-work with SoC functional emulation team to work out SoC emulation plan. Co-work with Debug tool and validation team to release emulation deliverables. Co-work with AMD Central DFX team to enhance emulation flow. PREFERRED EXPERIENCE: Solid background on process, device or ASIC design. Strong technical background in Verilog coding and testbench development. Experience in FPGA or Emulation will be a strong plus. Experience in System Verilog and UVM will be a strong plus. Good knowledge on DFT Scan/BIST will be a strong plus. Proven knowledge and expertise on two or more fields of SCAN, MBIST, RTL design, STA and DV. Strong programming and scripting skills in Perl, Tcl or Python will be a strong plus. Good communication skills (both English and Mandarin) and self-driven, willing to learn/share. ACADEMIC CREDENTIALS: Master degree LOCATION: Shanghai #LI-DNI Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Qualifications

Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Responsibilities

（如已在BOSS直聘投递，请勿在此重复投递） THE ROLE: This engineer plays a key role in SoC DV and Emulation flow, he/she will mainly focus on emulation model based testbench development and emulation test case verification to accelerate long run time simulation tasks in pre-silicon design stage. Moreover, he/she is expected to support post-silicon validation team to enable the silicon debug feature for silicon bring up tasks. THE PERSON: Good team worker with solid Verilog RTL design and verification knowledge/experience. Knowledge reservation on System_Verilog/UVM/Modeling/Scan/BIST will be a strong plus. KEY RESPONSIBILITIES: Cutting-edge test strategies study and implementation. SoC level DFT emulation testbench setup and maintenance Responsible for emulation model development and Pre-silicon test case simulation. Support Post-silicon validation bring up/debug tasks. Support part of SoC DFX DV verification tasks. Generate and maintain SoC DFT Emulation Checklist, keep enhancing emulation flow maturity. Co-work with SoC functional emulation team to work out SoC emulation plan. Co-work with Debug tool and validation team to release emulation deliverables. Co-work with AMD Central DFX team to enhance emulation flow. PREFERRED EXPERIENCE: Solid background on process, device or ASIC design. Strong technical background in Verilog coding and testbench development. Experience in FPGA or Emulation will be a strong plus. Experience in System Verilog and UVM will be a strong plus. Good knowledge on DFT Scan/BIST will be a strong plus. Proven knowledge and expertise on two or more fields of SCAN, MBIST, RTL design, STA and DV. Strong programming and scripting skills in Perl, Tcl or Python will be a strong plus. Good communication skills (both English and Mandarin) and self-driven, willing to learn/share. ACADEMIC CREDENTIALS: Master degree LOCATION: Shanghai #LI-DNI