Mixed Signal Analog Circuit Designer (RDSS Intern)
NVIDIA
On-site 🏢 12 November
R&D, Innovation
Hsinchu, Taiwan 🇹🇼 Taipei, Taiwan 🇹🇼
We are looking for a Mixed-Signal / Analog Circuit Designer – someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed mixed-signal circuit designs. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence.
What you'll be doing:
Be part of an analog team developing high-speed chip interfaces and complex analog functions that enable our graphics processing units (GPU) and SoC products (Tegra)
Design state-of-the-art mixed-signal circuits in deep sub-micron CMOS technologies.
Work closely with physical/layout engineers to floorplan and implement physical design of these functions.
Support debug, characterization and support product through high-volume production.
If you have the dream to learn and explore new technologies and have good analytical skills, this is the ideal position for you.
What we need to see:
You have a MSEE or PhD in Electrical Engineering.
Proven understanding of analog circuit layout concepts in submicron CMOS technologies
You have interests in more than one of the following areas: digital links for display interfaces (such as HDMI, LVDS, DVI, MIPI PHY, Display Port), USB, low-jitter clock synthesis using PLL techniques, IO pads, high-speed serial links, and ADC.
Able to communicate in spoken and written English
Work effectively in a team, good communication skills, enthusiasm and positive energy.
Proficiency in scripting languages like perl, python, skill etc.
Experience with design and verification tools (Cadence's IC design environment, analog circuit simulation tools like HSpice, Finesim, XA)
You are an expert with Cadence custom circuit design tools - particularly virtuoso
Experience running and debugging DRC and LVS with verification tools
We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.
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On-site 🏢 10 August
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Remote 🌎🌍🌏 02 December
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Washington, United States 🇺🇸
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Ontario, Canada 🇨🇦
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On-site 🏢 10 August
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Hybrid 🏡🏢 26 November
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On-site 🏢 10 August
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Casablanca, Morocco 🇲🇦
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Casablanca, Morocco 🇲🇦
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On-site 🏢 31 October
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California, United States 🇺🇸
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Hybrid 🏡🏢 15 November
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Karnataka, India 🇮🇳
Research Assistant - PFE 2025
On-site 🏢 10 August
R&D, Innovation
Casablanca, Morocco 🇲🇦
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On-site 🏢 28 October
R&D, Innovation
California, United States 🇺🇸
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Hybrid 🏡🏢 22 November
R&D, Innovation
Washington, United States 🇺🇸
PhD Research Intern, Large Language Models - 2025
Remote 🌎🌍🌏 21 October
R&D, Innovation
California, United States 🇺🇸 Remote, United States 🇺🇸
Research Intern - MSR Intelligent Networked Systems
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Ontario, Canada 🇨🇦
Power Methodology and Modeling Engineer - New College Grad 2024
On-site 🏢 04 November
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California, United States 🇺🇸 Texas, United States 🇺🇸
2025 Summer Intern: R&D (TDC/Life Science)
On-site 🏢 02 August
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Texas, United States 🇺🇸 New York, United States 🇺🇸 Illinois, United States 🇺🇸
Research Intern - MSR Inclusive Futures Team
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